Tables

• ​Table 1 Document Flow​

• ​Table 2 Terminology​

• ​Table 3 Reference Documents​

• ​Table 4 Architecture Stages​

Stage I

• ​Table 5 Stage I Firmware Volumes​

• ​Table 6 Stage I FV and Component Layout​

• ​Table 7 Stage I UEFI Components Platform Architecture Libraries​

• ​Table 8 Stage I Libraries​

• ​Table 9 Stage I SEC Functions​

• ​Table 10 Stage I PEI Functions​

• ​Table 11 Stage I Flash Map Configuration PCDs​

• ​Table 12 Stage I Debug Configuration​

• ​Table 13 Stage I Build Files​

• ​Table 14 Stage I Test Point Results​

Stage II

• ​Table 15 Stage II Firmware Volumes​

• ​Table 16 Stage II FV and Component Layout​

• ​Table 17 Stage II DXE UEFI Components​

• ​Table 18 Stage II PEI Platform Architecture Libraries​

• ​Table 19 Stage II DXE Platform Architecture Libraries​

• ​Table 20 Stage II PEI Functions​

• ​Table 21 Stage II Interfaces​

• ​Table 22 Stage II FSP Related Configuration​

• ​Table 23 Stage II FV Related Configuration​

• ​Table 24 Silicon Policy Libraries​

• ​Table 25 Stage II Build Files​

• ​Table 26 Test Point Results​

Stage III

• ​Table 27 Stage III Firmware Volumes​

• ​Table 28 Stage III FV and Component Layouts​

• ​Table 29 Stage III DXE UEFI Components​

• ​Table 30 Stage III Platform Architecture Libraries​

• ​Table 31 Stage III Required PEI Functions​

• ​Table 32 Stage III PEI Functions​

• ​Table 33 Stage III DXE Functions​

• ​Table 34 Stage III DXE Interfaces​

• ​Table 35 Stage III Flash Map Configuration PCDs​

• ​Table 36 Stage III Driver Configuration​

• ​Table 37 Stage III Build Files​

• ​Table 38 Stage III Test Point Results​

Stage IV

• ​Table 39 Stage IV Firmware Volumes​

• ​Table 40 Stage IV FV and Component Layout​

• ​Table 41 Stage IV ACPI DXE UEFI Components​

• ​Table 42 Stage IV DXE UEFI Components​

• ​Table 43 Stage IV SMM UEFI Components​

• ​Table 44 Stage IV Platform Architecture Libraries​

• ​Table 45 Stage IV DXE Functions​

• ​Table 46 Stage IV DXE Interfaces​

• ​Table 47 Stage IV SMM Functions​

• ​Table 48 Stage IV SMM Interfaces​

• ​Table 49 Memory Type Information Configuration​

• ​Table 50 Flash Map Configuration PCDs​

• ​Table 51 Stage IV Build Files​

• ​Table 52 Stage IV Test Point Results​

Stage V

• ​Table 53 Stage V Firmware Volumes​

• ​Table 54 Stage V FV and Components Layout​

• ​Table 55 Stage V PEI UEFI Components​

• ​Table 56 Stage V DXE UEFI Components​

• ​Table 57 Stage V SMM UEFI Components​

• ​Table 58 Stage V Platform Architecture Libraries​

• ​Table 59 Stage V PEI Functions​

• ​Table 60 Stage V DXE Functions​

• ​Table 61 Stage V SMM Functions​

• ​Table 62 Stage V Security Configuration​

• ​Table 63 Stage V Flash Map Configuration PCDs​

• ​Table 64 Stage V Feature Configuration​

• ​Table 65 Stage V Build Files​

• ​Table 66 Stage V Test Point Results​

Stage VI

• ​Table 67 Stage VI Firmware Volumes​

• ​Table 68 Stage VI FV and Component Layout​

• ​Table 69 Stage VI Flash Map Configuration PCDs​

• ​Table 70 Advanced Feature Template​

Appendix

• ​Table 71 Full Firmware Volume Layout​

• ​Table 72 Key Function Invocation​