9 Stage VII: Tuning

Note: This is a proposed stage in the architecture and this section is reserved for future completion and definition of the stage. Any implementation may ignore this stage until this section is completed and this notice is removed.
It is anticipated that future versions of this architecture specification will provide details for embedded performance tuning, common component tuning, and more invasive customization. The objective for this section is to provide a spectrum of options that keep as many board designs as consistent as possible. Some potential topics follow, but should not be reviewed at this
In Stage VII, the fully featured is tuned for production.
First, it can be worthwhile to look at the embedded features and performance oriented options that have been designed into the core or minimum platform. For example, if you do not support network boot, the PciBus driver provides a PCD to disable dispatching the network option ROM. By default, network option ROM dispatch is enabled. This is a known tunable setting.
Second, it can be worthwhile to strip unused components from the defined FV. For simplicity and consistency of progressing through Stage VI, it is better to use the provided code consistent with the architecture. Once a stable and fully functional system is completed, it is intended that platform architecture compatible systems can still remove unneeded components in order to finely tune the product. The core provides a tool named FMMT that can be used to process the build output and remove unnecessary components. Alternatively, a board can copy and modify the provided Build DSC and FDF files in the MinPlatformPkg and SiliconPkg. The former increases build time. The latter increases integration effort for new core, MinPlatformPkg, and SiliconPkg releases.
Third, it is often necessary to enable and use tools to perform detailed analysis of performance and size to identify hotspots that need to be improved.